Ultra-shallow semiconductor junctions are formed by ion implantation of dopant impurities into a semiconductor crystalline material. Such junctions consist of a P-type doped region interfacing with an N-type doped region of the semiconductor material, so that such junctions may be referred to as PN junctions. The ion implantation process places most of the implanted dopant atoms into interstitial sites in the semiconductor crystal lattice and damage from the ion implant process transforms much of the semiconductor material from a crystalline to an amorphous state. At this point, therefore, the implanted dopant atoms are not chemically bonded with the silicon atoms of the wafer surface and therefore do not significantly affect the properties of the material, until the material is re-crystallized and the implanted atoms are somehow moved to substitutional sites in the crystal lattice. Returning the semiconductor material to its crystalline state and moving the implanted dopant atoms into substitutional sites in the crystal lattice requires a post ion implant annealing step. The best post-implant annealing process, particularly for devices with feature sizes smaller than 65 nm, is dynamic surface annealing. Dynamic surface annealing uses a single intense laser beam from an array of coherent CW lasers formed as a thin (10's or 100's of microns wide) long beam. This beam scanned in the direction of its narrow dimension across the wafer surface, typically in a raster pattern for example, until the entire wafer surface has been scanned. This process is preferred above all others because the wafer temperature is elevated to re-crystallization levels (e.g., near the melting temperature of the semiconductor material) over an extremely small zone that moves with the scanning of the beam. This zone is confined approximately to the width of the narrow line beam and to a below-surface depth in the wafer of only 10's of microns. The bulk of the wafer remains at a much cooler temperature so that each region is immediately cooled to its prior (ambient) temperature as soon as the laser beam moves beyond the region. Moreover, each point on the wafer surface is raised to the re-crystallization (near melting) temperature for an extremely short amount of time (e.g., a few milliseconds) before being immediately cooled back to its ambient temperature by conduction to the surrounding bulk of the wafer. As a result, diffusion or movement of the implanted dopant atoms is reduced to the smallest average distance heretofore attained, thus solving a fundamental problem in the fabrication of below-65 nanometer semiconductor devices.
One problem inherent in the dynamic surface anneal process is that the extremely narrow surface region illuminated by the intense line beam expands and bulges relative to the remainder of the surface, thereby creating significant stress in the underlying thin film structures. One problem this creates is that the stress in the interface between the gate insulator (the thin gate oxide) and the underlying semiconductor layer (the source-drain channel) increases defects in the bonds between the silicon dioxide material of the gate insulator and the underlying crystalline silicon material. These defects correspond to surface states in the gate oxide-silicon interface that interact with charge flowing in the source-drain channel and thereby detract from the device performance. Increasing the number of such defects, or density of surface states detracts from device performance. The surface state density is measured by well-known techniques involving an observation of the change in capacitance across the gate oxide-silicon interface with applied voltage. The problem with the dynamic surface anneal process is that the surface state density increases as the result of the stresses arising during annealing, and specifically from the stress of the expansion of the narrow illuminated portion of the wafer surface. There has seemed to be no way of avoiding this problem.